Accelerate verification for the most complex chip designs. Scale custom silicon.
NORMAL EDA
AI-accelerated co-design for silicon engineering teams.
Structured representations of the chip
The Ontology grounds downstream collateral generation in a source of truth.
%20(1)%201.webp)
Intelligent Verification Planning
Normal EDA structures its understanding of specification documents into a hierarchical test plan with traceability between source docs and tests.
%201.webp)
Generate Stimulus
Convert the test cases into System Verilog stimulus, run simulations, and track coverage within Normal CLI.
%204.webp)
Normal EDA builds an understanding of your design intent and uses it to generate, verify, and optimize engineering artifacts — learning continuously from your team's feedback.
NORMAL ASICs
Normal’s physics-based ASICs relax the assumptions made in traditional computing, allowing for stochastic, stateful, and asynchronous computing, unlocking orders-of-magnitude more efficient compute.
As Normal EDA makes the chip design process look more like software, Normal ASICs explores what that new paradigm makes possible - applying AI to silicon and silicon to AI to enable ultra efficient ASICs for every workload.
THE CO-DESIGN ERA
We envision a world where software and silicon share the same physics, fundamentally changing how hardware is built.
Hardware
applications
We believe that ASICs of the future will converge with physics. Cutting-edge GenAI models already look like dynamical equations of physical systems. The most effective hardware will be built to reflect those same principles.
The semiconductor industry’s leading companies use Normal EDA to scale new hardware and enable 2x faster time-to-market
