Time Horizon

I came to this problem from quantum computing. I led a team at Los Alamos National Laboratory during the NISQ era, the era of noisy intermediate-scale quantum devices that opened in 2016 when IBM put its first quantum computer online. The expectation was that NISQ devices would transform chemistry, optimization, and finance. Ten years later, they have not made a commercial dent in any of them. Quantum will make its impact eventually, on a longer timeline than the field hoped, and the expectations that gathered around NISQ are now gathering around fault tolerance. The NISQ bet started from a hardware primitive and went searching for algorithms to fit it. I left because the AI revolution is happening now, and I always felt that if new physics was going to matter for AI, it had to arrive in this decade.

A Better Approach

In 2022 the two fields were moving at visibly different speeds. Text-to-image models arrived early in the year, text-to-text at the end of it, first Galactica briefly and then ChatGPT, and the progress in AI was shocking. The lack of progress in quantum hardware was just as obvious. We were far away from quantum advantage, and I was seeing it firsthand.

That mismatch is why Normal exists. The founders, out of Google X and Google Brain, refused the bottom-up path of perfecting qubits first and finding the relevance to AI later, and went straight at hardware that targets AI. From the beginning, the target was diffusion models, thermodynamic-inspired algorithms that were the state of the art for text-to-image in 2022: Stable Diffusion is named after them.

At Normal we came at the hardware question top-down. The gains we are after are orders of magnitude, which requires a different answer to what computation is: dropping an assumption the abstraction is built on, and only the workload can tell you which one. The goal is the world's best AI inference engine, across text, image, and video. We derived the efficiency requirements diffusion imposes and built silicon around them: we taped out our first chip, CN101, in July 2025 specifically to test these ideas.

Most of the industry's intuition about making AI faster comes from large language models: add parallelism, quantize the weights, scale memory bandwidth. Those levers work because of what transformer inference actually is. Autoregressive decoding is dominated by moving weights from memory to the compute units, which makes LLM serving memory-bandwidth-bound, and it is why cutting weight precision can roughly double effective throughput.

Workload-Hardware Alignment

LLMs run well on GPUs because model and hardware have been co-designed to each other; diffusion has had no such co-design. Those levers transfer to it far less cleanly than is commonly assumed, and the requirements that fall out of the workload look very different from a next-generation GPU. The stakes are highest at data center scale, where long-context decoding and diffusion inference increasingly run on the same GPU fleets built for transformer throughput, and the economics are already visible: OpenAI shut down Sora in March after inference costs that Forbes estimated at $15 million a day at peak ran against $2.1 million in total lifetime revenue. A diffusion workload priced by hardware built for LLMs is an example of that failure mode. Even the best-matched pairing is rationed: OpenAI staggered GPT-4.5's launch because, as Sam Altman put it, the company was "out of GPUs", and Altman has told the U.S. Senate that the cost of AI "will converge to the cost of energy", its abundance limited by the abundance of energy.

Making an impact this decade also means hardware that reaches users seamlessly: the same models, the same tools, a different backend, so that using it feels like software. Quantum fails that test by asking users to wait. Some other unconventional approaches like probabilistic bits repeat the pattern, requiring users to train new models suited to the hardware. We build for the models people already run.

We started with diffusion because the mismatch is easiest to see; in LLM inference it is hidden in the memory traffic that dominates the cost. Diffusion models are unusually expressive distribution learners over continuous spaces: images, video, and physical trajectories rather than discrete token vocabularies. Most of the hardware of the last five years is inherently discrete. Diffusion is where the mismatch is widest: a probabilistic workload on hardware engineered to be deterministic.

Proof in Silicon

The data center is becoming heterogeneous. The hyperscalers proved the case first: Google's TPUs, Amazon's Inferentia, and Meta's MTIA each showed that hardware co-designed for the dominant workload of its era beats general-purpose silicon on cost and efficiency. At GTC this spring Jensen Huang compressed the industry's economics into a single equation: revenue equals tokens per watt times available gigawatts. AI workloads are shifting toward inference, and inference sharpens the trade between general-purpose and purpose-built silicon: a GPU must serve training and inference, scientific computing and graphics, workloads that demand guaranteed precision and reliability, while AI generative models are probabilistic, so they tolerate randomness and lack of precision. Nvidia itself now splits inference across specialized silicon, compute-heavy parts for the context phase and bandwidth-heavy parts for generation, an approach it calls disaggregated inference. The endpoint is a data center running hundreds of different chips, each matched to its workload.

The stochastic workload class, algorithms that use randomness as part of the computation and tolerate approximation, has had no purpose-built silicon, and a conventional digital ASIC would close only part of the gap, because the deeper costs are properties of the digital-deterministic abstraction itself, whatever workload it targets. Escaping them required a different substrate.

In early 2023 we published Thermodynamic AI and the Fluctuation Frontier, which unifies diffusion, Bayesian neural networks, Monte Carlo methods, and simulated annealing under one framework, all accelerable by a single class of stochastic hardware. Conventional hardware pays for determinism three times over: energy suppressing the physical randomness of the substrate, more energy generating pseudo-randomness in software for the noise terms these algorithms require, and energy and latency on lockstep synchronization that probabilistic semantics never needed. Hardware that treats stochasticity as a native resource skips all three, and diffusion is the clearest case: its governing equation ends in white noise, so the hardware's own noise is absorbed into a term the algorithm requires anyway. Noise tolerance is a fourth design axis, after speed, energy, and area, one the industry has not yet used.

We coined the term physics-based ASICs to describe a class of hardware that relaxes conventional constraints, detailed in "Solving the compute crisis with physics-based ASICs" (arXiv, July 2025), written with our collaborators at ARIA, UC Santa Barbara, Penn, Cornell, Yale, and the Santa Fe Institute.

Normal taped out CN101, the world's first thermodynamic computing chip, in July 2025, months after we published the first experimental thermodynamic computer in Nature Communications. Where this earlier prototype was built from analog circuits on a printed circuit board, CN101 was the first implementation of thermodynamic computing in digital CMOS, manufacturable with standard processes and running its tiles asynchronously on independent local clocks, and it generalizes the paradigm beyond the linear algebra and Bayesian problems that earlier thermodynamic computers could encode in Gaussian form.

In results we are presenting at Hot Chips 2026, CN101 validates thermodynamic linear algebra in digital form and runs generative models natively on-chip. A conditional variational autoencoder generates MNIST digits on a single chip, and a convolutional flow-matching model generates CIFAR-10 images across six chips running as one system, reproducing the floating-point reference at a pixel error near 0.06. The generation is a hundred layers deep, a ten-layer network unrolled over ten integration steps, and the chips relax every layer together, reaching the same image in 62x fewer cycles than running the layers one after another.

These are small-scale results, and they validate the primitives: probabilistic state evolution in digital CMOS composes into working generative models, and the architecture scales in both directions, since adding chips reduces wall clock time and averaging across chips improves output quality.

Being a stochastic digital computer, CN101 required a careful mathematical formalism to run stochastic differential equations. We developed lattice random walk (LRW) discretisation (recently accepted for publication in npj Unconventional Computing) for this purpose. LRW has the same convergence guarantees as the standard Euler-Maruyama discretisation of SDEs, but it is specifically tailored to our hardware.

Quanta surveyed this field in July 2026. Speaking with them, I described it as designing computers that exploit thermodynamics as a computational resource, and the survey traces the same inversion, from thermal fluctuation as the thing engineers spend energy suppressing to thermal fluctuation as the thing performing the computation. It separates the two branches of the approach: systems that relax into an energy minimum encoding the answer, and systems held away from equilibrium where the trajectory itself is the calculation. Ours is the second, because a nonequilibrium device can be designed to finish on a set timescale, without waiting for natural equilibration. Our prototype and CN101 are covered there alongside the rest of the field's early silicon.

Looking Ahead

Our goal is to build the world's best AI inference engine: text, image, and video generation on one machine, and it will take multiple unconventional techniques. Match the hardware to diffusion and it has to be stochastic analog computation; match it to LLM decoding and it has to be computing inside the memory. Joined, they are stochastic analog computation in memory, and that is the architecture we are building.

What connects the two is state. Computation has a physical state, and conventional hardware spends its time and energy taking that state out of memory, transforming it, and putting it back. We control the dynamics of the state where it sits: the trajectory of the physical system is the computation.

We are targeting workloads across generative AI and beyond: generation in every modality, Monte Carlo methods, Bayesian neural networks that quantify the uncertainty in their predictions, and the multi-modal and world modeling workloads behind physical AI. All of these workloads are iterative and use randomness as part of the computation.

Our current focus is LLM inference. Decoding is memory-bound, its cost dominated by moving weights, and the attention cache grows with every token of context. Most people do not appreciate that LLM inference also involves randomness: every output token is drawn from a distribution.

Our architecture limits the movement instead of accelerating it. Thermo processing-with-memory runs a model's heaviest operations inside the memory itself: our current reference systems run models up to 128B parameters, and at rack scale the architecture targets transformer attention computed in memory for models up to a trillion parameters. Processing-in-memory is a long-pursued answer to this bottleneck, and the historical obstacle is noise: analog computation in the array degrades conventional numerics. The thermodynamic primitive treats that noise as the computational resource, and that is how we break through the memory wall.

Quantum has spent a decade as hardware in search of a workload. In AI, the workload came first, and we are building the hardware to meet it. What remains is engineering, and I'm confident we can deliver it in this decade.